1. 命令行编译

vcs / -sverilog/ +define+SYNOPSYS_SV/ -ntb_define NTB/ -ntb_opts rvm / -ntb_opts use_sigprop / -ntb_opts dw_vip / -ntb_vipext .ov / +define+NTB / +incdir+${include_dir}/verilog+${include_dir}/svtb+${scenario_dir}/svtb / -ntb_incdir ${scenario_dir}/svtb / -ntb_incdir ${include_dir}/vera+${src_dir}/vera / +pkgdir+${include_dir}/svtb / -f hdl_files / +vpdfile+vpdplus.vpd -vcd vcdplus.vcd 其中 hdl_files 有: =================================================== = AhbSlave_rvm.pkg = AhbMonitor_rvm.pkg = AhbMaster_rvm.pkg = AhbBus_rvm.pkg = ${scenario_dir}/svtb/ahb_rvm_sys_tst_svtb.v // toplevel = ${scenario_dir}/svtb/ahb_rvm_sys_tst.sv // test stimulus ===================================================